1. Field of the Invention
The present invention generally relates to an information processing device equipped with a cache memory used by a central processing unit (CPU). Examples of such an information processing device are a microprocessor and a microcomputer.
2. Description of the Related Art
FIG. 1 is a block diagram of a first conventional information processing device, which is made up of a CPU 1, an address bus 2 for transferring an address signal output by the CPU 1, and a cache memory 3 used by the CPU 1. The cache memory 3 is equipped with a hit/miss decision circuit 4 which determines whether an access to the cache memory 3 from the CPU 1 is a cache hit or a cache miss. An address bus 5 for transferring an address signal for an external address output from the cache memory 3 extends from the cache memory 3. An external access request signal line 6 which transfers an external access request signal output from the cache memory 3 extends from the cache memory 3.
Generally, a control register for an external resource, which may be a DMA (Direct Memory Access) controller, is designed so that the contents thereof can be changed without the CPU 1. Hence, it is difficult to ensure coherency to the cache memory 3. Hence, in an information processing device as described above, generally, an address area in which information that cannot be written into the cache memory 3 by an instruction access by the CPU 1 is stored is defined as a non-cachable area. For example, the control register for an external resource is defined as the non-cachable area.
The cache memory 3 is configured so as to refer to an address tag rather than determine whether an access from the CPU 1 is directed to the non-cachable area. Hence, when it is determined that the access is addressed to the non-cachable area, the access is determined as the cache miss in the cache memory 3, and thereafter an external access is carried out.
FIG. 2 is a timing chart of an operation in the case where an access to the cache memory 3 by the CPU 1 is addressed to a non-cachable area in the cache memory 3. Part (A) of FIG. 2 shows clock signals xcfx861 and xcfx862 having respective phases and serving as operation clocks. Part (B) of FIG. 2 shows a cache access address output to the cache memory 3 from the CPU 1. Part (C) of FIG. 2 shows an address tag look-up operation in the cache memory 3 in which a high level corresponds to the active state). Part (D) of FIG. 2 shows an external access address output from the cache memory 3, and part (E) thereof shows an external access request signal output from the cache memory 3 (a high level thereof is the active level).
When the CPU 1 accesses the cache memory 3, the cache access address is output to the cache memory 3 from the CPU 1. Upon receipt of the cache access address, the address tag regarding the cache access address is looked up in the cache memory 3 without determining whether the access from the CPU 1 is addressed to the non-cachable area. If the access from the CPU 1 is addressed to the non-cachable area, the hit/miss decision circuit 4 determines that the access is a cache miss. Then, the external access address for accessing an external memory is output from the cache memory 3, and the external address request signal for requesting an access to the external memory is switched to the high level.
As described above, in the first device shown in FIG. 1, the access to the non-cachable area in the cache memory 3 from the CPU 1 is processed so that the hit/miss decision circuit 4 determines that the access is a cache miss and thereafter the external access is performed.
FIG. 3 is a block diagram of a second conventional information processing device, which includes a CPU 8, an address bus 9 for transferring an address signal output by the CPU 8, and a cache memory unit 10 used by the CPU 8. The cache memory unit 10 is equipped with a hit/miss decision circuit which the access from the CPU 8 is a cache hit or a cache miss. The cache memory unit 10 is further equipped with a cachable area/non-cachable area decision circuit 12. The circuit 12 has the function of determining in which one of address areas among address areas partitioned beforehand the address area of the access requested by the CPU 8 falls. Further, the circuit 12 has the function of determining whether the address area of the access requested by the CPU 8 is a cachable area by referring to a cachable area/non-cachable area indicating register (not shown) which has data indicating whether the address area of the access requested by the CPU 8 is a cachable area. The cache memory unit 10 has an OR circuit 13, which performs an OR operation on the output signal of the hit/miss decision circuit 11 and the output signal of the decision circuit 12.
The hit/miss decision circuit 11 switches its output signal to a low level when the access from the CPU 8 is a cache hit, and switches the output signal to the high level when the access is a cache miss. The decision circuit 12 switches its output signal to the low level when the access from the CPU 8 is addressed to the cachable area, and switches the output signal to the high level when the access is addressed to the non-cachable area. In short, the cache memory unit 10 determines whether the access from the CPU 8 is a cache hit and whether the above access is addressed to the cachable area.
An address bus 14 that transfers the address signal for an external address output from the cache memory unit 10 extends from the cache memory unit 10. An external access request signal line 15 that transfers an external access request signal output from the cache memory unit 10 extends from the cache memory unit 10.
FIG. 4 is a timing chart of an operation in a case where an access to the cache memory unit 10 by the CPU 8 is addressed to a non-cachable area in the second conventional device. Part (A) of FIG. 4 shows clock signals xcfx861 and xcfx862 having respective phases and serving as operation clocks. Part (B) of FIG. 4 shows a cache access address output to the cache memory 3 from the CPU 1. Part (C) of FIG. 4 shows an address tag look-up operation in the cache memory 3 in which a high level corresponds to the active state). Part (D) of FIG. 4 shows an address area decision operation on the access requested by the CPU 8, the operation being performed in the cache memory unit 10 (the high level of the signal shown in part (D) is the active state). Part (E) of FIG. 4 shows a cachable area/non-cachable area indicating register loop-up operation in the cache memory unit 10 (the high level of the signal shown in part (E) is the active state). Part (F) of FIG. 4 shows the external access address output from the cache memory unit 10. Part (G) of FIG. 4 shows the external access request signal output from the cache memory unit 10 (the high level is the active level).
When the CPU 8 accesses the cache memory unit 10, the CPU 8 outputs the cache access address to the cache memory unit 10. Upon receipt of the cache access address, the decision circuit 12 in the cache memory unit 10 makes a decision on the address area of the access requested by the CPU 8. Subsequently, the cachable area/non-cachable area indicating register 12 is referred to, and the address area accessed by the CPU 8 is addressed to the cachable area. Further, in the cache memory unit 10, the address tag is looked up independently of the decision operation on the accessed address area and the register loop-up operation.
When the decision circuit 12 determines that the access from the CPU 8 is addressed to the non-cachable area, the output of the decision circuit 12 is switched to the high level before the hit/miss decision circuit 11 switches its output signal to the high level. As a result, the external access address for an external access is output from the cache memory unit 10, and the external access request signal is switched to the high level.
As described above, in the second conventional device, the access to the non-cachable area from the CPU 8 can be determined as an access to the non-cachable area by means of the decision circuit 12 xc2xd cycle before the access is determined as a cache miss by means of the hit/miss decision circuit 11. Hence, when the cache-inhibit area is accessed by the CPU 8, the external access can be advanced by xc2xd cycle.
FIG. 5 is a block diagram of a third conventional device, which includes a CPU 17, address buses 18 and 19, data buses 20 and 21, a cache memory unit 22 having a block transfer function, and a peripheral circuit 24 which may be a serial I/O. A main memory 23 is connected, as an external device, to the information processing device. The block transfer function transfers a group of blocks, e.g., four blocks at one time.
When a data read request to the cache memory unit 22 is issued by the CPU 17, the requested data is transferred to the CPU 17 from the cache memory unit 22 via the data bus 20 if the requested data is in the cache memory unit 22 (in the case of cache hit). If the requested data is not in the cache memory unit 22 (in the case of cache miss), a block transfer of data is performed.
FIG. 6 is a timing chart of the block transfer operation of the third conventional device. FIGS. 7 and 8 are block diagrams of the block transfer operation of the third conventional device. These figures relate to a case where a read access to the cache memory unit 22, for example, address A00, while data D00 is not present at address A00 of the cache memory unit 22.
At the commencement of the block transfer operation, as shown in FIGS. 6 and 7, the read access to address A00 is given to the main memory 23 by the CPU 17. Hence, data D00 of address A00 is output from the main memory 23 and transferred to the cache memory unit 22 and the CPU 17. Thereafter, as shown in FIGS. 6 and 8, read accesses to addresses A01, A02 and A03 are sequentially performed from the cache memory unit 22 to the main memory 23, and data D01, D02 and D03 of addresses A01, A02 and A03 are transferred to the cache memory unit 22.
The CPU 17 is in the waiting state until data D00 related to the data read request issued for itself. When data D00 is transferred and received, the CPU 17 proceeds with an operation on data D00 in parallel with the block transfer operation in the cache memory unit 22.
However, the above first, second and third conventional devices have the following respective problems.
As to the first device shown in FIG. 1, the external access is not allowed until the loop-up operation of the address tag is completed and the access is determined as a cache miss when the CPU 1 accesses a non-cachable area in the cache memory unit 3. Hence, it takes a long time to start the external access. Further, the address tag is referred to each time the CPU 1 accesses the cache memory unit 3. This leads to an increase in power consumption.
As to the second device shown in FIG. 3, as compared with the first device, the external access can be started by xc2xd cycle when an access to the cache memory unit 10 by the CPU 8 is addressed to a non-cachable area. However, the address area indicated by the access request by the CPU 8 is started after the cache access address from the CPU 8 is received. As a result, there is not sufficient time between the completion of the cachable area/non-cachable area indication register look-up operation and the start of the external access operation. The interval between the completion of the cachable area/non-cachable area indication register look-up operation and the start of the external access operation and becomes a critical path, which prevents speeding-up of the operation of the device. Further, the address tag is referred to each time the CPU 8 accesses the cache memory unit 10, as in the case of the first device. This leads to an increase in power consumption.
The problems of the third device are as follows. The operation on data D00 in the CPU 17 and the block transfer of data D01, D02 and D03 from the main memory 23 to the cache memory unit 22 are concurrently carried out. In this case, the address bus 19 and the data bus 21 are occupied by the cache memory unit 22. If an access to the peripheral circuit by address A10 is needed by the CPU 17 while the block transfer operation on data D01, D02 and D03 is being performed from the main memory 23 to the cache memory unit 22, address A10 is output by the CPU 17 as shown in FIG. 6. However, the CPU 17 cannot be allowed to access the peripheral circuit 24 until the block transferring of data D01, D02 and D03 from the main memory 23 to the cache memory unit 22 is completed. Hence, it takes a long time to obtain data D10 via the peripheral circuit 24 and hence the processing speed is reduced.
It is a general object of the present invention to provide an information processing device in which the above problems are eliminated.
A more specific object of the present invention is to provide an information processing device capable of operating at a higher speed.
The above objects of the present invention are achieved by an information processing device comprising:
a central processing unit;
a cache memory unit;
a first decision circuit which identifies one of partitioned address areas to be accessed before the central processing unit accesses the cache memory unit; and
a second decision circuit which determines whether the above one of the partitioned address areas is a cachable area or a non-cachable area before address tag data is referred to in the cache memory unit.
According to one aspect, the first decision circuit is provided in the central processing unit; and the second decision circuit is provided in the cache memory unit.
According to another aspect, the first decision circuit and the second decision circuit are provided in the cache memory unit.
The above objects of the present invention are also achieved by an information processing device comprising:
a central processing unit;
a cache memory unit having a block transfer function in which blocks of data are transferred; and
a peripheral circuit connected to an address bus and a data bus, which connect the central processing unit and the cache memory unit together.
According to one aspect, the cache memory unit includes a plurality of memory parts, each of which can be set to either a cache memory mode or a RAM mode.